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? semiconductor components industries, llc, 2005 september, 2005 ? rev. 9 1 publication order number: MC33260/d MC33260 greenline compact power factor controller: innovative circuit for cost effective solutions the MC33260 is a controller for power factor correction preconverters meeting internati onal standard requirements in electronic ballast and off?line power conversion applications. designed to drive a free frequency discontinuous mode, it can also be synchronized and in any case, it features very ef fective protections that ensure a safe and reliable operation. this circuit is also optimized to offer extremely compact and cost effective pfc solutions. while it requires a minimum number of external components, the MC33260 can control the follower boost operation that is an innovative mode allowing a drastic size reduction of both the inductor and the power switch. ultimately, the solution system cost is significantly lowered. also able to function in a traditional way (constant output voltage regulation level), any intermed iary solutions can be easily implemented. this flexibility makes it ideal to optimally cope with a wide range of applications. general features ? standard constant output voltage or ?follower boost? mode ? switch mode operation: voltage mode ? latching pwm for cycle?by?cycle on?time control ? constant on?time operation that saves the use of an extra multiplier ? totem pole output gate drive ? undervoltage lockout with hysteresis ? low startup and operating current ? improved regulation block dynamic behavior ? synchronization capability ? internally trimmed reference current source ? pb?free packages are available safety features ? overvoltage protection: output overvoltage detection ? undervoltage protection: protection against open loop ? effective zero current detection ? accurate and adjustable maximum on?time limitation ? overcurrent protection ? esd protection on each pin figure 1. typical application 8 filtering capacitor l1 ct m1 d1 d1...d4 v cc c1 + sync v control r ocp r cs r o 7 6 5 1 2 3 4 load (smps, lamp ballast,...) MC33260 dip?8 configuration shown http://onsemi.com MC33260p pin connections 18 7 6 5 2 3 4 feedback input v control oscillator capacitor (c t ) v cc current sense input synchronization input gnd gate drive pdip?8 p suffix case 626 1 8 so?8 d suffix case 751 1 8 marking diagrams 33260 alyw 1 8 MC33260p awl yywwg 1 8 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week g or = pb?free package 18 7 6 5 2 3 4 feedback input v control oscillator capacitor (c t ) v cc current sense input synchronization input gnd gate drive MC33260d see detailed ordering and shipping information in the package dimensions section on page 20 of this data sheet. ordering information
MC33260 http://onsemi.com 2 figure 2. block diagram 15 pf 11 v current mirror current mirror i o i o i o i ref 11 v 300 k v reg r r r ? + ct fb v o v control regulator enable 11 v/8.5 v synchro arrangement 11 v r r rq q s pwm latch thstdwn ? + 11 v leb ? + output_ctrl ? + ? + ?60 mv i uvp ovp uvp i ovph /i ovpl i cs (205 a) synchro v cc drive gnd output_ctrl MC33260 current sense v ref i ref 0 1 0 1 pwm comparator output_ctrl i o 1.5 v 97%i ref i ref v ref i o i osc ? ch = i ref 2 x i o x i o
MC33260 http://onsemi.com 3 maximum ratings rating pin # pdip?8 pin # so?8 symbol value unit gate drive current* source sink 7 5 i o(source) i o(sink) ?500 500 ma v cc maximum voltage 8 6 (vcc) max 16 v input voltage v in ?0.3 to +10 v power dissipation and thermal characteristics p suffix, pdip package maximum power dissipation @ t a = 85 c thermal resistance junction?to?air p d r ja 600 100 mw c/w operating junction temperature t j 150 c operating ambient temperature t a ?40 to +105 c maximum ratings are those values beyond which device damage can occur. maximum ratings applied to the device are individual str ess limit values (not normal operating conditions) and are not valid simultaneously. if these limits are exceeded, device functional operation i s not implied, damage may occur and reliability may be affected. electrical characteristics (v cc = 13 v, t j = 25 c for typical values, t j = ?40 to 105 c for min/max values unless otherwise noted.) characteristic pin # pdip?8 pin # so?8 symbol min typ max unit gate drive section gate drive resistor source resistor @ i drive = 100 ma sink resistor @ i drive = 100 ma 7 5 r ol r oh 10 5 20 10 35 25 gate drive voltage rise time (from 3.0 v up to 9.0 v) (note 1) 7 5 t r ? 50 ? ns output voltage falling time (from 9.0 v down to 3.0 v) (note 1) 7 5 t f ? 50 ? ns oscillator section maximum oscillator swing 3 1 v t 1.4 1.5 1.6 v charge current @ i fb = 100 a 3 1 i charge 87.5 100 112.5 a charge current @ i fb = 200 a 3 1 i charge 350 400 450 a ratio multiplier gain over maximum swing @ i fb = 100 a 3 1 k osc 5600 6400 7200 1/(v.a) ratio multiplier gain over maximum swing @ i fb = 200 a 3 1 k osc 5600 6400 7200 1/(v.a) average internal oscillator pin capacitance over oscillator maximum swing (c t voltage varying from 0 up to 1.5 v) (note 2) 3 1 c int 10 15 20 pf discharge time (c t = 1.0 nf) 3 1 t disch ? 0.5 1.0 s regulation section regulation high current reference 1 7 i regh 192 200 208 a ratio (regulation low current reference) / i regh 1 7 i regl /i regh 0.965 0.97 0.98 ? v control impedance 1 7 z vcontrol ? 300 ? k note: i fb is the current that is drawn by the feedback input pin. 1. 1.0 nf being connected between the pin 7 and ground for pdip?8, between pin 5 and ground for so?8. 2. guaranteed by design.
MC33260 http://onsemi.com 4 electrical characteristics (v cc = 13 v, t j = 25 c for typical values, t j = ?40 to 105 c for min/max values unless otherwise noted.) characteristic pin # pdip?8 pin # so?8 symbol min typ max unit regulation section (continued) feedback pin clamp voltage @ i fb = 100 a 1 7 v fb?100 1.5 2.1 2.5 v feedback pin clamp voltage @ i fb = 200 a 1 7 v fb?200 2.0 2.6 3.0 v current sense section zero current detection comparator threshold 4 2 v zcd?th ?90 ?60 ?30 mv negative clamp level (i cs?pin = ?1.0 ma) 4 2 cl?neg ? ?0.7 ? v bias current @ vcs = v zcd?th 4 2 i b?cs ?0.2 ? ? a propagation delay (vcs > v zcd?th ) to gate drive high 7 5 t zcd ? 500 ? ns current sense pin internal current source 4 2 i ocp 192 205 218 a leading edge blanking duration leb ? 400 ? ns overcurrent protection propagation delay (vcs < v zcd?th to gate drive low) 7 5 t ocp 100 160 240 ns synchronization section synchronization threshold pdip?8 so?8 5 ? ? 3 v sync?th v sync?th 0.8 0.8 1.0 1.0 1.2 1.4 v v negative clamp level (i sync = ?1.0 ma) 5 3 cl?neg ? ?0.7 ? v minimum off?time 7 5 t off 1.5 2.1 2.7 s minimum required synchronization pulse duration 5 3 t sync ? ? 0.5 s overvoltage protection section overvoltage protection high current threshold and i regh difference 1 7 i ovph ?i regh 8.0 13 18 a overvoltage protection low current threshold and i regh difference 1 7 i ovpl ?i regh 0 ? ? ? ratio (i ovph /i ovpl ) 1 7 i ovph /i ovpl 1.02 ? ? ? propagation delay (i fb > 110% i ref to gate drive low) 7 5 t ovp ? 500 ? ns undervoltage protection section ratio (undervoltage protection current threshold) / i regh 1 7 i uvp /i regh 12 14 16 % propagation delay (i fb < 12% i ref to gate drive low) 7 5 t uvp ? 500 ? ns thermal shutdown section thermal shutdown threshold 7 5 t stdwn ? 150 ? c hysteresis 7 5 t stdwn ? 30 ? c v cc undervoltage lockout section startup threshold 8 6 v stup?th 9.7 11 12.3 v disable voltage after threshold turn?on 8 6 v disable 7.4 8.5 9.6 v total device power supply current startup (v cc = 5 v with v cc increasing) operating @ i fb = 200 a 8 6 i cc ? ? 0.1 4.0 0.25 8.0 ma note: vcs is the current sense pin voltage and i fb is the feedback pin current.
MC33260 http://onsemi.com 5 pin numbers are relevant to the pdip?8 version 0 3.5 20 40 60 80 100 120 140 160 180 200 220 240 0 0.5 1.0 1.5 2.0 2.5 3.0 junction temperature ( c) i pin1 : feedback current ( a) i pin1 : feedback current ( a) figure 3. regulation block output versus feedback current i pin1 : feedback current ( a) figure 4. regulation block output versus feedback current figure 5. maximum osc illator swing versus temperature figure 6. feedback i nput voltage versus feedback current figure 7. osc illator charge current versus feedback current figure 8. osc illator charge current versus temperature maximum oscillator swing (v) i , oscillator charge current ( a) osc?ch v : regulation block output (v) control feedback input voltage (v) v : regulation block output (v) control junction temperature ( c) i pin1 : feedback current ( a) 0 1.6 ?40 c 25 c 105 c 20 40 60 80 100 120 140 160 180 200 220 240 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 185 1.6 190 195 200 205 210 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1.340 ?40 ?20 0 20 40 60 80 100 1.335 1.330 1.325 1.320 1.315 1.310 1.305 1.300 0 500 20 40 60 80 100 120 140 160 180 200 220 240 0 50 100 150 200 250 300 350 400 450 ?40 410 ?20 0 20 40 60 80 100 405 400 395 390 385 i pin1 = 200 a ?40 c 25 c 105 c ?40 c 25 c 105 c ?40 c 25 c 105 c i , oscillator charge current ( a) osc?ch
MC33260 http://onsemi.com 6 pin numbers are relevant to the pdip?8 version ?40 0.150 ?40 207 30 120 50 75 ?40 104 on?time ( s) oscillator charge current ( a) figure 9. oscillator charge current versus temperature figure 10. on?time versus feedback current figure 11. on?time versus feedback current figure 12. internal current sources versus temperature figure 13. (i ovph /i ref ), (i ovpl /i ref ), (i regl /i ref ) versus temperature figure 14. undervoltage ratio versus temperature i pin1 : feedback current ( a) i pin1 : feedback current ( a) t j , junction temperature ( c) t j , junction temperature ( c) t j , junction temperature ( c) ?20 0 20 40 60 80 100 103 102 101 100 99 98 97 50 70 90 110 130 150 170 190 210 100 80 60 40 20 0 60 70 80 90 100 65 55 45 35 25 15 ?20 0 20 40 60 80 100 197 198 199 200 201 202 203 204 205 206 ?20 0 20 40 60 80 100 0.140 0.130 0.132 0.134 0.136 0.138 0.142 0.144 0.146 0.148 i pin1 = 100 a ?40 c 25 c 105 c 1 nf connected to pin 3 on?time ( s) ?40 c 25 c 105 c 1 nf connected to pin 3 i ocp i regh regulation and cs current source ( a) undervoltage ratio (i uvp /i ) ref ?40 1.07 t j , junction temperature ( c) ?20 0 20 40 60 80 100 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 1.06 (i ovph /i ref ), (i ovpl /i ref ), (i regl /i ref ) (i ovph /i ref ) (i ovpl /i ref ) (i regl /i ref )
MC33260 http://onsemi.com 7 pin numbers are relevant to the pdip?8 version ch1 1 0 4.5 0 20 ?40 ?54.8 v cc : supply voltage (v) v control : pin 2 voltage (v) figure 15. current sense threshold versus temperature figure 16. circuit consumption versus supply voltage figure 17. oscillator pin internal capacitance figure 18. gate drive cross conduction figure 19. gate drive cross conduction figure 20. gate drive cross conduction t j , junction temperature ( c) ?20 0 20 40 60 80 100 ?55 ?55.2 ?55.4 ?55.6 ?55.8 ?56 ?56.2 ?56.4 ?56.6 2 4 6 8 10 12 14 16 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 , circuit consumption (ma) i cc 0.2 0.4 0.6 0.8 1.0 1.2 1.4 15 10 5 0 oscillator pin internal capacitance (pf) current sense threshold (mv) ?40 c 25 c 105 c ?40 c 25 c 105 c 10.0 v ch2 2 10.0 mv m 1.00 s ch1 600 mv ch1 1 10.0 v ch2 2 10.0 mv m 1.00 s ch1 600 mv ch1 1 10.0 v ch2 2 10.0 mv m 1.00 s ch1 600 mv vgate i cross?cond (50 ma/div) 25 c v cc = 12 v c gate = 1 nf vgate i cross?cond (50 ma/div) 105 c v cc = 12 v c gate = 1 nf vgate i cross?cond (50 ma/div) ?40 c v cc = 12 v c gate = 1 nf
MC33260 http://onsemi.com 8 pin function description pin # pdip?8 pin # so?8 function description 1 7 feedback input this pin is designed to receive a current that is proportional to the preconverter output voltage. this information is used for both the regulation and the overvoltage and undervoltage protections. the current drawn by this pin is internally squared to be used as oscillator capacitor charge current. 2 8 v control this pin makes available the regulation block output. the capacitor connected between this pin and ground, adjusts the control bandwidth. it is typically set below 20 hz to obtain a nondistorted input current. 3 1 oscillator capacitor (c t ) the circuit uses an on?time control mode. this on?time is controlled by comparing the c t voltage to the v control voltage. c t is charged by the squared feedback current. 4 2 zero current detection input this pin is designed to receive a negative voltage signal proportional to the current flowing through the inductor. this information is generally built using a sense resistor. the zero current detection prevents any restart as long as the pin 4 voltage is below (?60 mv). this pin is also used to perform the peak current limitation. the overcurrent threshold is programmed by the resistor connected between the pin and the external current sense resistor. 5 3 synchronization input this pin is designed to receive a synchronization signal. for instance, it enables to synchronize the pfc preconverter to the associated smps. if not used, this pin must be grounded. 6 4 ground this pin must be connected to the preregulator ground. 7 5 gate drive the gate drive current capability is suited to drive an igbt or a power mosfet. 8 6 v cc this pin is the positive supply of the ic. the circuit turns on when v cc becomes higher than 11 v, the operating range after startup being 8.5 v up to 16 v. figure 21. application schematic 18 7 6 5 2 3 4 l1 filtering capacitor sync m1 c1 d1 + v control v cc load (smps, lamp ballast,...) r o ct r ocp r cs d1...d4 MC33260 dip?8 configuration shown
MC33260 http://onsemi.com 9 functional description pin numbers are relevant to the pdip?8 version introduction the need of meeting the requirements of legislation on line current harmonic content, results in an increasing demand for cost effective solutions to comply with the power factor regulations. this data sheet describes a monolithic controller specially designed for this purpose. most off?line appliances use a bridge rectifier associated to a huge bulk capacitor to derive raw dc voltage from the utility ac line. figure 22. typical circuit without pfc load converter rectifiers bulk storage capacitor + ac line this technique results in a high harmonic content and in poor power factor ratios. in effect, the simple rectification technique draws power from the mains when the instantaneous ac voltage exceeds the capacitor voltage. this occurs near the line voltage peak and results in a high charge current spike. consequently, a poor power factor (in the range of 0.5 ? 0.7) is generated, resulting in an apparent input power that is much higher than the real power. figure 23. line waveforms without pfc line sag rectified dc ac line voltage ac line current 0 0 v pk active solutions are the most popular way to meet the legislation requirements. they consist of inserting a pfc pre?regulator between the rectifier bridge and the bulk capacitor. this interface is, in fact, a step?up smps that outputs a constant voltage while drawing a sinusoidal current from the line. figure 24. pfc preconverter converter rectifiers + ac line load bulk storage capacitor high frequency bypass capacitor pfc preconverter MC33260 the MC33260 was developed to control an active solution with the goal of increasing its robustness while lowering its global cost. operation description the MC33260 is optimized to just as well drive a free running as a synchronized discontinuous voltage mode. it also features valuable protections (overvoltage and undervoltage protection, overcurrent limitation, ...) that make the pfc preregulator very safe and reliable while requiring very few external components. in particular, it is able to safely face any uncontrolled direct charges of the output capacitor from the mains which occur when the output voltage is lower than the input voltage (startup, overload, ...). in addition to the low count of elements, the circuit can control an innovative mode named ?follower boost? that permits to significantly reduce the size of the preconverter inductor and power mosfet. with this technique, the output regulation level is not forced to a constant value, but can vary according to the a.c. line amplitude and to the power. the gap between the output voltage and the ac line is then lowered, what allows the preconverter inductor and power mosfet size reduction. finally, this method brings a significant cost reduction. a description of the functional blocks is given below. regulation section connecting a resistor between the output voltage to be regulated and the pin 1, a feedback current is obtained. typically, this current is built by connecting a resistor between the output voltage and the pin 1. its value is then given by the following equation: i pin1 v o v pin1 r o where: r o is the feedback resistor, v o is the output voltage, v pin1 is the pin 1 clamp value. the feedback current is compared to the reference current so that the regulation block outputs a signal following the characteristic depicted in figure 25. according to the power and the input voltage, the output voltage regulation level varies between two values (v o ) regl and (v o ) regh corresponding to the i regl and i regh levels. figure 25. regulation characteristic 1.5 v regulation block output i o i regl (97%i ref ) i regh (i ref ) the feedback resistor must be chosen so that the feedback current should equal the internal current source i regh when the output voltage exceeds the chosen upper regulation voltage [(v o ) regh ].
MC33260 http://onsemi.com 10 pin numbers are relevant to the pdip?8 version r o v o regh v pin1 i regh consequently: in practice, v pin1 is small compared to (v o ) regh and this equation can be simplified as follows (i regh being also replaced by its typical value 200 a ): r o 5 v o regh ( k ) the regulation block output is connected to the pin 2 through a 300 k resistor. the pin 2 voltage (v control ) is compared to the oscillator sawtooth for pwm control. an external capacitor must be connected between pin 2 and ground, for external loop compensation. the bandwidth is typically set below 20 hz so that the regulation block output should be relatively constant over a given ac line cycle. this integration that results in a constant on?time over the ac line period, prevents the mains frequency output ripple from distorting the ac line current. oscillator section the oscillator consists of three phases: ? charge phase: the oscillator capacitor voltage grows up linearly from its bottom value (ground) until it exceeds v control (regulation block output voltage). at that moment, the pwm latch output gets low and the oscillator discharge sequence is set. ? discharge phase: the oscillator capacitor is abruptly discharged down to its valley value (0 v). ? waiting phase: at the end of the discharge sequence, the oscillator voltage is maintained in a low state until the pwm latch is set again. figure 26. oscillator i charge = 2 i o i o / i ref 0 1 ct 3 15 pf 0 1 output_ctrl the oscillator charge current is dependent on the feedback current (i o ). in effect i charge 2 i 2 o i ref where: i charge is the oscillator charge current, i o is the feedback current (drawn by pin 1), i ref is the internal reference current (200 a ). so, the oscillator charge current is linked to the output voltage level as follows: i charge 2 v o v pin1 2 r 2 o i ref where: v o is the output voltage, r o is the feedback resistor, v pin1 is the pin 1 clamp voltage. in practice, v pin1 that is in the range of 2.5 v, is very small compared to v o . the equation can then be simplified by neglecting v pin1 : i charge 2 v 2 o r 2 o i ref it must be noticed that the oscillator terminal (pin 3) has an internal capacitance (c int ) that varies versus the pin 3 voltage. over the oscillator swing, its average value typically equals 15 pf (min 10 pf, max 20 pf). the total oscillator capacitor is then the sum of the internal and external capacitors. c pin3 c t c int pwm latch section the MC33260 operates in voltage mode: the regulation block output (v control ? pin 2 voltage) is compared to the oscillator sawtooth so that the gate drive signal (pin 7) is high until the oscillator ramp exceeds v control . the on?time is then given by the following equation: t on c pin3 v control i ch where: t on is the on?time, c pin3 is the total oscillator capacitor (sum of the internal and external capacitor), i charge is the oscillator charge current (pin 3 current), v control is the pin 2 voltage (regulation block output). consequently, replacing i charge by the expression given in the oscillator section : t on r 2 o i ref c pin3 v control 2 v 2 o one can notice that the on?time depends on v o (preconverter output voltage) and that the on?time is maximum when vcontrol is maximum (1.5 v typically). at a given v o , the maximum on?time is then expressed by the following equation: t on max c pin3 r 2 o i ref v control max 2 v 2 o this equation can be simplified replacing 2 [( v control ) max *i ref ]
by k osc refer to electrical characteristics, oscillator section . then: t on max c pin3 r 2 o k osc v 2 o
MC33260 http://onsemi.com 11 pin numbers are relevant to the pdip?8 version this equation shows that the maximum on?time is inversely proportional to the squared output voltage. this property is used for follower boost operation (refer to follower boost section). current sense block the inductor current is converted into a voltage by inserting a ground referenced resistor (r cs ) in series with the input diodes bridge (and the input filtering capacitor). therefore a negative voltage proportional to the inductor current is built: v cs ? r cs i l where: i l is the inductor current, r cs is the current sense resistor, v cs is the measured r cs voltage. figure 27. current sensing v ocp ?60 mv zero current detection power switch drive inductor current rcs voltage pin 4 voltage time v ocp = r ocp i ocp an overcurrent is detected if v pin4 crosses the threshold (?60 mv) during the power switch on state the negative signal v cs is applied to the current sense through a resistor r ocp . the pin is internally protected by a negative clamp (?0.7 v) that prevents substrate injection. as long as the pin 4 voltage is lower than (?60 mv), the current sense comparator resets the pwm latch to force the gate drive signal low state. in that condition, the power mosfet cannot be on. during the on?time, the pin 4 information is used for the overcurrent limitation while it serves the zero current detection during the off time. zero current detection the zero current detection function guarantees that the mosfet cannot turn on as long as the inductor current hasn?t reached zero (discontinuous mode). the pin 4 voltage is simply compared to the (?60 mv) threshold so that as long as v cs is lower than this threshold, the circuit gate drive signal is kept in low state. consequently, no power mosfet turn on is possible until the inductor current is measured as smaller than (60 mv/r cs ) that is, the inductor current nearly equals zero. figure 28. current sense block 1 0 i ocp (205 a) output_ctrl leb ? + ?60 mv pwm latch r s q output_ctrl r 4 to output buffer (output_ctrl low <=> gate drive in low state) r ocp v ocp r cs d1...d4 overcurrent protection during the power switch conduction (i.e. when the gate drive pin voltage is high), a current source is applied to the pin 4. a voltage drop v ocp is then generated across the resistor r ocp that is connected between the sense resistor and the current sense pin (refer to figure 28). so, instead of v cs , the sum (v cs + v ocp ) is compared to (?60 mv) and the maximum permissible current is the solution of the following equation: ? r cs ipk max v ocp ?60 mv where: ipk max is maximum allowed current, r cs is the sensing resistor. the overcurrent threshold is then: ipk max r ocp i ocp 60 10 ?3 r cs where: r ocp is the resistor connected between the pin and the sensing resistor (r cs ), i ocp is the current supplied by the current sense pin when the gate drive signal is high (power switch conduction phase). i ocp equals 205 a typically. practically, the v ocp offset is high compared to 60 mv and the precedent equ ation can be simplified. the maximum current is then given by the following equation: ipk max r ocp ( k ) r cs ( ) 0.205 ( a ) consequently, the r ocp resistor can program the ocp level whatever the r cs value is. this gives a high freedom in the choice of r cs . in particular, the inrush resistor can be utilized.
MC33260 http://onsemi.com 12 pin numbers are relevant to the pdip?8 version figure 29. pwm latch pwm latch r s q q synchronization arrangement ? + ovp, uvp & ? + pwm latch comparator v control (v pin2 ? regulation output) output buffer 7 zcd & ocp current sense comparator ?60 mv oscillator sawtooth output_ctrl th?stdwn v cc 5 a leb (leading edge blanking) has been implemented. this circuitry disconnects the current sense comparator from pin 4 and disables it during the 400 first ns of the power switch conduction. this prevents the block from reacting on the current spikes that generally occur at power switch turn on. consequently, proper operation does not require any filtering capacitor on pin 4. protections ocp (overcurrent protection) refer to current sense block . ovp (overvoltage protection) the feedback current (i o ) is compared to a threshold current (i ovph ). if it exceeds this value, the gate drive signal is maintained low until this current gets lower than a second level (i ovpl ). figure 30. internal current thresholds gate drive enable v control i o i uvp i regl i ovph i ovpl i regh so, the ovp upper threshold is: v ovph v pin1 r o i ovph where: r o is the feedback resistor that is connected between pin 1 and the output voltage, i ovph is the internal upper ovp current threshold, v pin1 is the pin 1 clamp voltage. practically, v pin1 that is in the range of 2.5 v, can be neglected. the equation can then be simplified: v ovph r o ( m ) i ovph ( a )( v ) on the other hand, the ovp low threshold is: v ovpl v pin1 r o i ovpl where i ovpl is the internal low ovp current threshold. consequently, v pin1 being neglected: v ovpl r o ( m ) i ovpl ( a )( v ) the ovp hysteresis prevents erratic behavior. i ovpl is guaranteed to be higher than iregh (refer to parameters specification). this ensures that the ovp function doesn?t interfere with the regulation one. uvp (undervoltage protection) this function detects when the feedback current is lower than 14% of i ref . in this case, the pwm latch is reset and the power switch is kept off. this protection is useful to: ? protect the preregulator from working in too low mains conditions. ? to detect the feedback current absence (in case of a nonproper connection for instance). the uvp threshold is: v uvp v pin1 r o ( m ) i uvp ( a ) ( v ) practically (v pin1 being neglected), v uvp r o ( m ) i uvp ( a )( v ) maximum on?time limitation as explained in pwm latch , the maximum on?time is accurately controlled. pin protection all the pins are esd protected.
MC33260 http://onsemi.com 13 pin numbers are relevant to the pdip?8 version in particular, a 11 v zener diode is internally connected between the terminal and ground on the following pins: feedback, v control , oscillator, current sense, and synchronization. figure 31. synchronization arrangement s2 r2 q2 s1 r2 q1 & 2 s r sync ? + sync 5 1 v uvlo 1 v output_ctrl pwm latch set q1 high <=> synchronization mode synchronization block the MC33260 features two modes of operation: ? free running discontinuous mode: the power switch is turned on as soon as there is no current left in the inductor (zero current detection). this mode is simply obtained by grounding the synchronization terminal (pin 5). ? synchronization mode: this mode is set as soon as a signal crossing the 1.0 v threshold, is applied to the pin 5. in this case, operation in free running can only be recovered after a new circuit startup. in this mode, the power switch cannot turn on before the two following conditions are fulfilled. ? still, the zero current must have been detected. ? the precedent turn on must have been followed by (at least) one synchronization raising edge crossing the 1.0 v threshold. in other words, the synchronization acts to prolong the power switch off time. consequently, a proper synchronized operation requires that the current cycle (on?time + inductor demagnetization) is shorter than the synchronization period. practically, the inductor must be chosen accordingly. otherwise, the system will keep working in free running discontinuous mode. figure 36 illustrates this behavior. it must be noticed that whatever the mode is, a 2.0 s minimum of f?time is forced. this delay limits the switching frequency in light load conditions. output section the output stage contains a totem pole optimized to minimize the cross conduction current during high speed operation. the gate drive is kept in a sinking mode whenever the undervoltage lockout is active. the rise and fall times have been controlled to typically equal 50 ns while loaded by 1.0 nf. reference section an internal reference current source (i ref ) is trimmed to be 4% accurate over the temperature range (the typical value is 200 a). i ref is the reference used for the regulation (i regh = i ref ). undervoltage lockout section an undervoltage lockout comparator has been implemented to guarantee that the integrated circuit is operating only if its supply voltage (v cc ) is high enough to enable a proper working. the uvlo comparator monitors the pin 8 voltage and when it exceeds 11 v, the device gets active. to prevent erratic operation as the threshold is crossed, 2.5 v of hysteresis is provided. the circuit off state consumption is very low: in the range of 100 a @ v cc = 5.0 v. this consumption varies versus v cc as the circuit presents a resistive load in this mode. thermal shutdown an internal thermal circuitry is provided to disable the circuit gate drive and then to prevent it from oscillating, if the junction temperature exceeds 150 c typically. the output stage is again enabled when the temperature drops below 120 c typically (30 c hysteresis).
MC33260 http://onsemi.com 14 pin numbers are relevant to the pdip?8 version follower boost traditional pfc preconverters provide the load with a fixed and regulated voltage that gener ally equals 230 v or 400 v according to the mains type (u.s ., european, or universal). in the ?follower boost? operation, the preconverter output regulation level is not fixed but varies linearly versus the ac line amplitude at a given input power. figure 32. follower boost characteristics traditional output v o (follower boost) load v ac this technique aims at reducing the gap between the output and the input voltages to minimize the boost efficiency degradation. follower boost benefits the boost presents two phases: ? the on?time during which the power switch is on. the inductor current grows up linearly according to a slope (v in /l p ), where v in is the instantaneous input voltage and l p the inductor value. ? the off?time during which the power switch is off. the inductor current decreases linearly according the slope (v o ? v in )/l p , where v o is the output voltage. this sequence that terminates when the current equals zero, has a duration that is inversely proportional to the gap between the output and input voltages. consequently, the off?time duration becomes longer in follower boost. consequently, for a given peak inductor current, the longer the off time, the smaller power switch duty cycle and then its conduction dissipation. this is the first benefit of this technique: the mosfet on?time losses are reduced. the increase of the off time duration also results in a switching frequency diminution (for a given inductor value). given that in practise, the boost inductor is selected big enough to limit the switching frequency down to an acceptable level, one can immediately see the second benefit of the follower boost: it allows the use of smaller , lighter and cheaper inductors compared to traditional systems. finally, this technique utilization brings a drastic system cost reduction by lowering the size and then the cost of both the inductor and the power switch. the power switch is on the power switch is off il time ipk vout traditional preconverter follower boost preconverter vin vin vin vin il il figure 33. off?time duration increase follower boost implementation in the MC33260, the on?time is differently controlled according to the feedback current level. two areas can be defined: ? when the feedback current is higher than i regl (refer to regulation section), the regulation block output (v control ) is modulated to force the output voltage to a desired value. ? on the other hand, when the feedback current is lower than i regl , the regulation block output and therefore, the on?time are maximum. as explained in pwm latch section, the on?time is then inversely proportional to the output voltage square. the follower boost is active in these conditions in which the on?time is simply limited by the output voltage level. note: in this equation, the feedback pin voltage (v pin1 ) is neglected compared to the output voltage (refer to the pwm latch section). t on t on max c pin3 r 2 o k osc v 2 o where: c pin3 is the total oscillator capacitor (sum of the internal and external capacitors ? c int + c t ), k osc is the ratio (oscillator swing over oscillator gain), v o is the output voltage, r o is the feedback resistor.
MC33260 http://onsemi.com 15 pin numbers are relevant to the pdip?8 version on the other hand, the boost topology has its own rule that dictates the on?time necessary to deliver the required power: t on 4 l p p in v 2 pk where: v pk is the peak ac line voltage, l p is the inductor value, p in is the input power. combining the two equations, one can obtain the follower boost equation: v o r o 2 c pin3 k osc l p p in v pk consequently, a linear dependency links the output voltage to the ac line amplitude at a given input power. figure 34. follower boost characteristics the regulation block is active output voltage input power t on on?time v o p in output voltage input power t on = k/v o 2 v ac (v ac )max (v ac )min the behavior of the output voltage is depicted in figures 34 and 35. in particular, figure 35 illustrates how the output voltage converges to a stable equilibrium level. first, at a given ac line voltage, the on?time is dictated by the power demand. then, the follower boost characteristic makes correspond one output voltage level to this on?time. combining these two laws, it appears that the power level forces the output voltage. one can notice that the system is fully stable: ? if an output voltage increase makes it move away from its equilibrium value, the on?time will immediately diminish according to the follower boost law. this will result in a delivered power decrease. consequently, the supplied power being too low, the output voltage will decrease back, ? in the same way, if the output voltage decreases, more power will be transferred and then the output voltage will increase back. figure 35. follower boost output voltage v acll v ac v achl v ac v o regulation block is active v o = v pk p in (p in )min (p in )max non usable area mode selection the operation mode is simply selected by adjusting the oscillator capacitor value. as shown in figure 35, the output voltage first has an increasing linear characteristic versus the ac line magnitude and then is clamped down to the regulation value. in the traditional mode, the linear area must be rejected. this is achieved by dimensioning the oscillator capacitor so that the boost can deliver the maximum power while the output voltage equals its regulation level and this, whatever the given input voltage. practically, that means that whatever the power and input voltage conditions are, the follower boost would generate output voltages values higher than the regulation level, if there was no regulation block. in other words, if (v o ) regl is the low output regulation level: v o regl r o 2 c t c int k osc l p p in max v pk consequently, c t ?c int 4 k osc l p p in max v o 2 regl r 2 o v 2 pk using i regl (regulation block current reference), this equation can be simplified as follows: c t ?c int 4 k osc l p p in max i 2 regl v 2 pk in the follower boost case, the oscillator capacitor must be chosen so that the wished characteristics are obtained. consequently, the simple choice of the oscillator capacitor enables the mode selection.
MC33260 http://onsemi.com 16 figure 36. typical waveforms 2 s synchronization signal zero current detection 2 s delay 2 s 2 s 2 s v control 205 a oscillator circuit output i cs inductor current 3 4 1 2 case no. 1: the turn on is delayed by the zero current detection cases no. 2 and no. 3: the turn on is delayed by the synchronization signal case no. 4: the turn on is delayed by the minimum off?time (2 s)
MC33260 http://onsemi.com 17 main design equations (note 3) rms input current (i ac ) i ac p o v ac (preconverter efficiency) is generally in the range of 90 ? 95%. maximum inductor peak current ((i pk )max): (i pk ) max 2 2 (p o ) max v acll (i pk )max is the maximum inductor current. output voltage peak to peak 100hz (120hz) ripple (( vo)pk?pk): ( v o ) pk?pk p o 2 f ac c o v o f ac is the ac line frequency (50 or 60hz). inductor value (l p ): l p 2 t v o 2 v acll v acll 2 v o v acll (i pk ) max t is the maximum switching period. (t = 40 s) for universal mains operation and (t = 20 s) for narrow range are generally used. maximum power mosfet conduction losses ((p on )max): (p on ) max 1 3 (rds)on (i pk ) max 2 1 1.2 v acll v o (rds)on is the mosfet drain source on?time resistor. in follower boost, the ratio (v acll /v o ) is higher. the on?time mosfet losses are then reduced. maximum average diode current (i d ): (i d ) max (p o ) max (v o ) min the average diode current depends on the power and on the output voltage. current sense resistor losses (pr cs ): pr cs 1 6 (rds)on (i pk ) 2 max this formula indicates the required dissipation capability for r cs (current sense resistor). over current protection resistor (r ocp ): r ocp r cs (i pk ) max 0.205 (k ) the overcurrent threshold is adjusted by r ocp at a given r cs . r cs can be a preconverter inrush resistor. oscillator external capacitor value (c t ): ?traditional operation c t c int 2 k osc l p (p in ) max i 2 regl v 2 ac the follower boost characteristic is adjusted by the c t choice. the traditional mode is also selected by c t . c int is the oscillator pin internal capacitor. ? follower boost: v o r o 2 c t c int k osc l p p in v pk feedback resistor (r o ): r o (v o ) reg v fb i regh v o 200 (m ) the output voltage regulation level is adjusted by r o . 3. the preconverter design requires the following characteristics specification: ? (v o ) reg : desired output voltage regulation level ? ( v o ) pk?pk : admissible output peak to peak ripple voltage ? p o : desired output power ? v ac : ac rms operating line voltage ? v acll : minimum ac rms operating line voltage ? v fb : feedback pin voltage
MC33260 http://onsemi.com 18 figure 37. 80 w wide mains power factor corrector c2 47 f 450 v d5 + 80 w load (smps, lamp ballast,...) r1 1 m 0.25 w emi filter 15 k /0.25 w r2 1 m 0.25 w mur460e 1n4007 d1 d2 d4 d3 r4 1 /2 w r3 c1 330 nf 500 vdc q1 mtp4n50e l1 320 h 90 to 270 vac 22 /0.25 w r5 feedback block ? + i ocp (205 a) ? + pwm latch synchronization block s r q q regulator enable i ref v ref 11 v/8.5 v output thstdwn ? + c4 330 pf synchro gnd drive v cc pwm comp i ref i o i ref i o c3 680 nf 300 k i o 1.5 v 97%.i ref i ref v reg output ct v control i o current sense block regulation block output buffer v prot MC33260 ?60 mv v reg oscillator 15 pf i oscCch 2x|0x|0 i ref leb 0 1 1 0 uvp, ovp v prot i o i ovpl i ovph i uvp (? ? ?) l1: coilcraft n2881 ? a (primary: 62 turns of # 22 awg ? secondary: 5 turns of # 22 awg core: coilcraft pt2510, ee 25 l1: gap: 0.072 total for a primary inductance (lp) of 320 h) feedback input power factor controller test data* ac line input dc output current harmonic distortion (% i fund ) v rms (v) p in (w) pf (?) i fund (ma) thd h2 h3 h5 h7 h9 v o (v) v o (v) i o (ma) p o (w) (%) 90 88.2 0.991 990 8.1 0.07 5.9 4.3 1.5 1.7 181 31.2 440 79.6 90.2 110 86.3 0.996 782 7.0 0.05 2.7 5.7 1.1 0.8 222 26.4 360 79.9 92.6 135 85.2 0.995 642 8.2 0.03 1.5 6.8 1.1 1.5 265 20.8 300 79.5 93.3 180 87.0 0.994 480 9.5 0.16 4.0 6.5 3.1 4.0 360 16.0 225 81.0 93.1 220 84.7 0.982 385 15 0.5 8.4 7.8 5.3 1.9 379 14.0 210 79.6 94.4 240 85.3 0.975 359 16.5 0.7 9.0 7.8 7.4 3.8 384 14.0 210 80.6 94.5 260 84.0 0.967 330 18.8 0.7 11.0 7.0 9.0 4.0 392 13.2 205 80.4 95.7 *measurements performed using voltech pm1200 ac power analysis.
MC33260 http://onsemi.com 19 figure 38. circuit supply voltage 18 7 6 5 2 3 4 MC33260 d1...d4 + v cc 15 v c pin8 + r r stup pdip?8 configuration shown MC33260 v cc supply voltage in some applications, the arrangement shown in figure 38 must be implemented to supply the circuit. a startup resistor is connected between the rectified voltage (or one?half wave) to charge the MC33260 v cc up to its startup threshold (11 v typically). the MC33260 turns on and the v cc capacitor (c pin8 ) starts to be charged by the pfc transformer auxiliary winding. a resistor , r (in the range of 22 ) and a 15 v zener should be added to protect the circuit from excessive voltages. when the pfc preconverter is loaded by an smps, the MC33260 should preferably be supplied by the smps itself. in this configuration, the smps starts first and the pfc gets active when the MC33260 v cc supplied by the power supply, exceeds the device startup level. with this configuration, the pfc preconverter doesn?t require any auxiliary winding and finally a simple coil can be used. pcb layout the connections of the oscillator and v control capacitors should be as short as possible. figure 39. preconverter loaded by a flyback smps: MC33260 v cc supply 18 7 6 5 2 3 4 MC33260 v cc smps driver + ++ ++ + preconverter output + dip?8 configuration shown
MC33260 http://onsemi.com 20 ordering information device package shipping ? MC33260p pdip?8 50 units / rail MC33260pg pdip?8 (pb?free) 50 units / rail MC33260d soic?8 98 units / rail MC33260dg soic?8 (pb?free) 98 units / rail MC33260dr2 soic?8 2500 units / tape & reel MC33260dr2g soic?8 (pb?free) 2500 units / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. package dimensions pdip?8 p suffix plastic package case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m ??? 10 ??? 10 n 0.76 1.01 0.030 0.040
MC33260 http://onsemi.com 21 package dimensions soic?8 case 751?07 issue ag seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
MC33260 http://onsemi.com 22 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 MC33260/d the product described herein (MC33260), may be covered by one or more of the following u.s. patents: 5,073,850; 6,177,782. there may be other patents pending. greenline is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 61312, phoenix, arizona 85082?1312 usa phone : 480?829?7710 or 800?344?3860 toll free usa/canada fax : 480?829?7709 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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